Counterclockwise: CPU cores grow not just in numbers, but in variety too

07 July 2019
The "big-little" designs grew into "big-medium-little" to keep heat and power usage in check while maintaining the capability to go full throttle.

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Anonymous, 08 Jul 2019Lol, Apple A12 Bionic craps all over Snapdragons. Smooth 60... moreFamous throttling issues.
Apple Bionic is like Usain Bolt.
Good on short terms running bt when running marathon he dies early.

  • Anonymous

User, 08 Jul 2019Qualcomm's Snapdragon processor is the best.Lol, Apple A12 Bionic craps all over Snapdragons. Smooth 60FPS gaming consistently.

  • Anonymous

CptPower, 08 Jul 2019Well no this crashed same way like Meizu Zero. Thanks

Anonymous, 08 Jul 2019Whatever happened with these people? They keep saying this... moreWell no this crashed same way like Meizu Zero.

  • Anonymous

Ryan D, 08 Jul 2019Companies which develops chips are actually fooling us ,The... moreCompanies were developing their own versions of ARM under license as well, not just using design cells.

  • Anonymous

CptPower, 07 Jul 2019Well this getting interesting. I remember Turning Monolith... moreWhatever happened with these people? They keep saying this or that, but did they ever release anything?

  • Anonymous

Denis Thomas, 07 Jul 2019We are talking about mobile processors. And believe or not,... morePointing out reality. What I've pointed to is superior low energy processor technology suitable to produce and ARM kicking processor. We can write about mediocre processors and notches etc, or you can peel back the onion, and publish an article on what's next. We have lost our guts nowadays, it's all arm this arm that, oh it has .1 ghz more, gray suite this gray suite that, oh look out, it's Apple in their black suite this, black suite that, with a little gray suite underneath where the ARM is. The mobile industry has become a line of iMacs. Android is designed to be a virtual operating system that can run on new types of processors.


  • Anonymous

Anonymous, 07 Jul 2019What the hell did you just say? The 10-20Ghz with simplified processor, or the 100,000's of simplified CPU/GPU processors in the same space as a modern big die? They are both likely I think. You could with advanced technique and manufacturing process and good cooling tech in and on chip. It would be still a fraction of the switching rate they get experimental silicon processes to run in the past. Once you put a complex chip and timing circuits together the different parts add delay slowing it down. Less complexity just gives some advantage, but you are not going pack them in, they are likely to be far apart for cooling. Per active transistor they could be a magnitude leakier than a 2 Ghz arm, plus pack as many of them in to make the same transistor count as an i7 it might just melt on the spot with the best desktop cooler and not be economical to cool.

I'm not looking at putting hundreds of thousands of 20Ghz CPU's on one chip, if that's what you mean. I'm hoping that a silicon process with a native clocking speed close to 5Ghz comes out, then to pack memory around each to further reduce heat density.


  • Anonymous

Anonymous, 07 Jul 2019Arm is not dated at all,A cam even exist for next 50 years ... moreI often get somebody blunder in and try this stuff. If you went to Wikipedia even, you will see Risc-V is NOT the 1990's but this decade. A project that examined the deficiencies of past RISC processors (including Arm) and came up with an more optimised solution. Despite whatever maybe adopted from the past, it's start date proper is thus decade. Now, ARM is from the early 1980's and has been expanded. ARM has actually have introduced multiple alternative instruction sets for efficiency over the original instruction set stream.
As a non optimised instruction set expands they can try to add further instructions and work arounds to make it work better, as with x86 and ARM.

So, RISC-V was designed from scratch for better optimisation than the original ARM instruction set stream. Notice, I did not compare it to the newer alternative (thumb etc) instruction sets the ARM company has continued to develop. I think that is where ARM is going as Risc-V gathers steam.

https://en.m.wikipedia.org/wiki/RISC-V

Now, the premise of Risc-V in itself is a faulty one. It tries to optimise for non optimal coding system. Unix and C is often the root of these errors. X86 is optimised for this sort of code (but I would say more windows variation) and is enormous, while we look at 4000 transistors plus for a CPU. You might notice I'm talking about people designing actual CPU's and doing ISA design myself to high efficiency. You might think we actually know something, before not doing your home work and trying to school us!

Ryan D, 08 Jul 2019Physically there are only two cores divides in clusters ,an... moreAnd there no compulsion that size of each should be equal

Popy, 07 Jul 20191- A76 (High Frequency) + 3 - A76 (Medium Frequency) + 3 A5... morePhysically there are only two cores divides in clusters ,and they are free to play with clock sleeps ,so they overclock or under lock it . It's like two slices of bread ,cut in four pieces each..

Companies which develops chips are actually fooling us ,They all buy the architecture from ARM ,and since its impossible for everyone to develop the same design on account of breaching patent issue ,they just play with clock speeds and cores . Physically there are only two cores divides in clusters ,and they are free to play with clock sleeps ,so they overclock or under lock it . It's like two slices of bread ,cut in four pieces each

  • User

Qualcomm's Snapdragon processor is the best.

  • Moj

Popy, 07 Jul 20191- A76 (High Frequency) + 3 - A76 (Medium Frequency) + 3 A5... moreNope not gonna happen!
But the idea is good!

1- A76 (High Frequency) + 3 - A76 (Medium Frequency) + 3 A53 ( Low frequency) + 1 A35 ( very low frequency ) how about this design?

  • Anonymous

ZolaIII, 07 Jul 2019Well we will be going back to two cluster design from the n... moreThat's interesting.

Well we will be going back to two cluster design from the next year based on new Neoverse N1, E1 core's and a increase in a core count to 10~12 core's. It will be significant for baseline user experience as E1 is according to ARM projections faster than A72 - A73 even when not using SMT while enough power efficient to replace A55's (on leading edge node's). E1 is designed to fit in DinamiQ cluster which N1 goes with it's own two to four core's per cluster design with much better caches coherence & true output compared to the A76 as a first real true ARM server design. The Neuvers isn't designed for mobile per se but even N1 is easier to same with bigger L2, L3 cache to fit in in comparison to A77 (as it's still 4 vs 6 IPC wide).

Well this getting interesting.
I remember Turning Monolith Chaconne a phablet with 3x SD835 inside for 1600 bucks 18GB of RAM and 4TB disk space and thats a phablet.

More specs here.
https://www.gadgetsnow.com/mobile-phones/Turing-Monolith-Chaconne

Anonymous, 07 Jul 2019What is the article for? Maybe it is better to write one a... moreWe are talking about mobile processors. And believe or not, if everyone wants Arm Qualcomm's processors, then they are the best in the business.

What are you trying to pull here?

  • Anonymous

Anonymous, 07 Jul 2019What is the article for? Maybe it is better to write one a... moreWhat the hell did you just say?